RGMII_LINK_STA_P=No_Pending, RX_OVERFLOW_P=no_pending, TX_DMA_STOPPED_P=no_pending, TX_P=no_pending, RX_EARLY_P=no_pending, TX_TIMEOUT_P=no_pending, TX_EARLY_P=no_pending, TX_BUF_UA_P=no_pending, RX_TIMEOUT_P=no_pending, RX_BUF_UA_P=no_pending, TX_UNDERFLOW_P=no_pending, RX_P=no_pending
EMAC Interrupt Status Register
| TX_P | Frame Transmission Interrupt Pending 0 (no_pending): undefined 1 (pending): undefined |
| TX_DMA_STOPPED_P | Transmission DMA Stopped Interrupt Pending 0 (no_pending): undefined 1 (pending): undefined |
| TX_BUF_UA_P | TX Buffer UA Interrupt Pending 0 (no_pending): undefined 1 (pending): undefined |
| TX_TIMEOUT_P | Transmitter Timeout Interrupt Pending 0 (no_pending): undefined 1 (pending): undefined |
| TX_UNDERFLOW_P | TX FIFO Underflow Interrupt Pending 0 (no_pending): undefined 1 (pending): undefined |
| TX_EARLY_P | Total interrupt pending which the frame is transmitted to FIFO 0 (no_pending): undefined 1 (pending): undefined |
| RX_P | Frame RX Completed Interrupt Pending 0 (no_pending): undefined 1 (pending): undefined |
| RX_BUF_UA_P | RX Buffer UA Interrupt Pending 0 (no_pending): undefined 1 (pending): undefined |
| RX_DMA_STOPPED_P | When this bit asserted, the RX DMA FSM is stopped. |
| RX_TIMEOUT_P | RX Timeout Interrupt Pending 0 (no_pending): undefined 1 (pending): undefined |
| RX_OVERFLOW_P | RX FIFO Overflow Error Interrupt Pending 0 (no_pending): undefined 1 (pending): undefined |
| RX_EARLY_P | RX DMA Filled First Data Buffer of the Receive Frame Interrupt Pending 0 (no_pending): undefined 1 (pending): undefined |
| RGMII_LINK_STA_P | RMII Link Status Changed Interrupt Pending 0 (No_Pending): undefined 1 (Pending): undefined |