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Allwinner /D1H /EMAC /EMAC_MII_CMD

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Interpret as EMAC_MII_CMD

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MII_BUSY)MII_BUSY 0 (R)MII_WR 0PHY_REG_ADDR 0PHY_ADDR0 (R16)MDC_DIV_RATIO_M

MDC_DIV_RATIO_M=R16, MII_WR=R

Description

EMAC Management Interface Command Register

Fields

MII_BUSY

MII Status
MII_WR

MII Write and Read

0 ®: undefined

1 (W): undefined
PHY_REG_ADDR

PHY Register Address
PHY_ADDR

PHY Address
MDC_DIV_RATIO_M

MDC Clock DIvider Ratio

0 (R16): undefined

1 (R32): undefined

2 (R64): undefined

3 (R128): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data