RX_ERR_FRM=drop, RX_FLOW_CTL_TH_ACT=FM1K, RX_FLOW_CTL_TH_DEACT=FM1K, RX_EMA_EN=stop, RX_MD=greater_than_th, FLUSH_RX_FRM=enable, RX_TH=T64, RX_FIFO_FLOW_CTL=disable
EMAC Receive Control Register1
| FLUSH_RX_FRM | Flush Receive Frames 0 (enable): undefined 1 (disable): undefined |
| RX_MD | Receive Mode 0 (greater_than_th): undefined 1 (locate_full_frame): undefined |
| RX_RUNT_FRM | |
| RX_ERR_FRM | 0 (drop): undefined 1 (forward): undefined |
| RX_TH | Threshold for RX DMA FIFO Start 0 (T64): undefined 1 (T32): undefined 2 (T96): undefined 3 (T128): undefined |
| RX_FLOW_CTL_TH_ACT | Threshold for Activating Flow Control 0 (FM1K): undefined 1 (FM2K): undefined 2 (FM3K): undefined 3 (FM4K): undefined |
| RX_FLOW_CTL_TH_DEACT | Threshold for Deactivating Flow Control 0 (FM1K): undefined 1 (FM2K): undefined 2 (FM3K): undefined 3 (FM4K): undefined |
| RX_FIFO_FLOW_CTL | Receive FIFO Flow Control Enable 0 (disable): undefined 1 (enable): undefined |
| RX_EMA_EN | Receive DMA Enable 0 (stop): undefined 1 (start): undefined |
| RX_DMA_START |