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Allwinner /D1H /GPIO /pb_eint_cfg1

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Interpret as pb_eint_cfg1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (positive_edge)EINT8_CFG

EINT10_CFG=positive_edge, EINT12_CFG=positive_edge, EINT9_CFG=positive_edge, EINT11_CFG=positive_edge, EINT8_CFG=positive_edge

Description

PB External Interrupt Configure Register 1

Fields

EINT10_CFG

External INT Mode

0 (positive_edge): undefined

1 (negative_edge): undefined

2 (high_level): undefined

3 (low_level): undefined

4 (double_edge): undefined
EINT12_CFG

External INT Mode

0 (positive_edge): undefined

1 (negative_edge): undefined

2 (high_level): undefined

3 (low_level): undefined

4 (double_edge): undefined
EINT9_CFG

External INT Mode

0 (positive_edge): undefined

1 (negative_edge): undefined

2 (high_level): undefined

3 (low_level): undefined

4 (double_edge): undefined
EINT11_CFG

External INT Mode

0 (positive_edge): undefined

1 (negative_edge): undefined

2 (high_level): undefined

3 (low_level): undefined

4 (double_edge): undefined
EINT8_CFG

External INT Mode

0 (positive_edge): undefined

1 (negative_edge): undefined

2 (high_level): undefined

3 (low_level): undefined

4 (double_edge): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data