Allwinner /D1H /GPIO /pb_eint_ctl

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Interpret as pb_eint_ctl

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disable)EINT7_CTL

EINT10_CTL=disable, EINT0_CTL=disable, EINT4_CTL=disable, EINT5_CTL=disable, EINT8_CTL=disable, EINT6_CTL=disable, EINT11_CTL=disable, EINT1_CTL=disable, EINT2_CTL=disable, EINT3_CTL=disable, EINT9_CTL=disable, EINT7_CTL=disable

Description

PB External Interrupt Control Register

Fields

EINT10_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined

EINT0_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined

EINT4_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined

EINT5_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined

EINT8_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined

EINT6_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined

EINT11_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined

EINT1_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined

EINT2_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined

EINT3_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined

EINT9_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined

EINT7_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined

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