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Allwinner /D1H /GPIO /pc_eint_ctl

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Interpret as pc_eint_ctl

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disable)EINT7_CTL

EINT4_CTL=disable, EINT1_CTL=disable, EINT0_CTL=disable, EINT6_CTL=disable, EINT2_CTL=disable, EINT3_CTL=disable, EINT5_CTL=disable, EINT7_CTL=disable

Description

PC External Interrupt Control Register

Fields

EINT4_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined
EINT1_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined
EINT0_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined
EINT6_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined
EINT2_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined
EINT3_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined
EINT5_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined
EINT7_CTL

External INT Enable

0 (disable): undefined

1 (enable): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data