RegViz: Visualize pd_eint

Allwinner /D1H /GPIO /pd_eint_ctl

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Interpret as pd_eint_ctl

EINT14_CTL=disable, EINT15_CTL=disable, EINT2_CTL=disable, EINT6_CTL=disable, EINT3_CTL=disable, EINT16_CTL=disable, EINT18_CTL=disable, EINT19_CTL=disable, EINT20_CTL=disable, EINT13_CTL=disable, EINT17_CTL=disable, EINT8_CTL=disable, EINT11_CTL=disable, EINT22_CTL=disable, EINT7_CTL=disable, EINT21_CTL=disable, EINT1_CTL=disable, EINT10_CTL=disable, EINT9_CTL=disable, EINT5_CTL=disable, EINT12_CTL=disable, EINT0_CTL=disable, EINT4_CTL=disable

Description

PD External Interrupt Control Register

Fields

EINT14_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT15_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT2_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT6_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT3_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT16_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT18_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT19_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT20_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT13_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT17_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT8_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT11_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT22_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT7_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT21_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT1_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT10_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT9_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT5_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT12_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT0_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined
EINT4_CTL	External INT Enable 0 (disable): undefined 1 (enable): undefined

Links

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