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Allwinner /D1H /GPIO /pg_eint_cfg2

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Interpret as pg_eint_cfg2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (positive_edge)EINT17_CFG

EINT18_CFG=positive_edge, EINT16_CFG=positive_edge, EINT17_CFG=positive_edge

Description

PG External Interrupt Configure Register 2

Fields

EINT18_CFG

External INT Mode

0 (positive_edge): undefined

1 (negative_edge): undefined

2 (high_level): undefined

3 (low_level): undefined

4 (double_edge): undefined
EINT16_CFG

External INT Mode

0 (positive_edge): undefined

1 (negative_edge): undefined

2 (high_level): undefined

3 (low_level): undefined

4 (double_edge): undefined
EINT17_CFG

External INT Mode

0 (positive_edge): undefined

1 (negative_edge): undefined

2 (high_level): undefined

3 (low_level): undefined

4 (double_edge): undefined

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data