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Allwinner /D1H /HSTimer /HS_TMR_IRQ_EN

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Interpret as HS_TMR_IRQ_EN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disabled)HS_TMR1_INT_EN

HS_TMR0_INT_EN=disabled, HS_TMR1_INT_EN=disabled

Description

HS Timer IRQ Enable Register

Fields

HS_TMR0_INT_EN

HSTimer Interrupt Enable

0 (disabled): undefined

1 (enabled): undefined
HS_TMR1_INT_EN

HSTimer Interrupt Enable

0 (disabled): undefined

1 (enabled): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data