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Allwinner /D1H /HSTimer /HS_TMR_IRQ_STAS

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Interpret as HS_TMR_IRQ_STAS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (no_effect)HS_TMR0_IRQ_PEND

HS_TMR1_IRQ_PEND=no_effect, HS_TMR0_IRQ_PEND=no_effect

Description

HS Timer Status Register

Fields

HS_TMR1_IRQ_PEND

HSTimer IRQ Pending

0 (no_effect): undefined

1 (pending): undefined
HS_TMR0_IRQ_PEND

HSTimer IRQ Pending

0 (no_effect): undefined

1 (pending): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data