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Allwinner /D1H /SYS_CFG /EMAC_EPHY_CLK0

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Interpret as EMAC_EPHY_CLK0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MII)ETCS 0 (MII)EPIT 0 (Disable)ETXIE 0 (Disable)ERXIE 0ERXDC0ETXDC0 (Disable)RMII_EN 0 (External)PHY_SELECT 0 (Power_up)SHUTDOWN 0 (High)LED_POL 0 (F25M)CLK_SEL 0PHY_ADDR0 (Normal)EPHY_MODE 0 (Internal)XMII_SEL 0BPS_EFUSE

ETCS=MII, XMII_SEL=Internal, EPHY_MODE=Normal, ETXIE=Disable, EPIT=MII, CLK_SEL=F25M, PHY_SELECT=External, RMII_EN=Disable, ERXIE=Disable, LED_POL=High, SHUTDOWN=Power_up

Description

EMAC-EPHY Clock Register 0

Fields

ETCS

0 (MII): undefined

1 (External_GMII_RGMII): undefined

2 (Internal_GMII_RGMII): undefined
EPIT

0 (MII): undefined

1 (RGMII): undefined
ETXIE

0 (Disable): undefined

1 (Enable): undefined
ERXIE

0 (Disable): undefined

1 (Enable): undefined
ERXDC
ETXDC
RMII_EN

0 (Disable): undefined

1 (Enable): undefined
PHY_SELECT

0 (External): undefined

1 (Internal): undefined
SHUTDOWN

0 (Power_up): undefined

1 (Shut_down): undefined
LED_POL

0 (High): undefined

1 (Low): undefined
CLK_SEL

0 (F25M): undefined

1 (F24M): undefined
PHY_ADDR
EPHY_MODE

0 (Normal): undefined

1 (Simulation): undefined

2 (AFE_Test): undefined
XMII_SEL

0 (Internal): undefined

1 (External): undefined
BPS_EFUSE

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data