Allwinner /D1H /TIMER /tmr1_ctrl

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Interpret as tmr1_ctrl

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (stop_pause)tmr_en 0 (no_effect)tmr_reload 0 (losc)tmr_clk_src 0 (P1)tmr_clk_pres 0 (periodic)tmr_mode

tmr_reload=no_effect, tmr_en=stop_pause, tmr_clk_pres=P1, tmr_clk_src=losc, tmr_mode=periodic

Description

Timer IRQ Enable Register

Fields

tmr_en

0 (stop_pause): undefined

1 (start): undefined

tmr_reload

0 (no_effect): undefined

1 (reload): undefined

tmr_clk_src

0 (losc): undefined

1 (osc24_m): undefined

tmr_clk_pres

0 (P1): undefined

1 (P2): undefined

2 (P4): undefined

3 (P8): undefined

4 (P16): undefined

5 (P32): undefined

6 (P64): undefined

7 (P128): undefined

tmr_mode

0 (periodic): undefined

1 (single_counting): undefined

Links

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