Regviz

Allwinner /D1H /TIMER /tmr_irq_en

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Interpret as tmr_irq_en

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disabled)tmr0_irq_en 0 (disabled)tmr1_irq_en

tmr1_irq_en=disabled, tmr0_irq_en=disabled

Description

Timer IRQ Enable Register

Fields

tmr0_irq_en

0 (disabled): undefined

1 (enabled): undefined
tmr1_irq_en

0 (disabled): undefined

1 (enabled): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data