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Allwinner /D1H /TIMER /tmr_irq_sta

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Interpret as tmr_irq_sta

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (no_effect)tmr0_irq_pend 0 (no_effect)tmr1_irq_pend

tmr1_irq_pend=no_effect, tmr0_irq_pend=no_effect

Description

Timer Status Register

Fields

tmr0_irq_pend

0 (no_effect): undefined

1 (pending): Indicates that the interval value of the timer 0 is reached. Write 1 to clear the pending status.
tmr1_irq_pend

0 (no_effect): undefined

1 (pending): Indicates that the interval value of the timer 1 is reached. Write 1 to clear the pending status.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data