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Atmel /AT91SAM9CN12 /AES /ISR

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Interpret as ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DATRDY)DATRDY 0 (URAD)URAD 0 (IDR_WR_PROCESSING)URAT

URAT=IDR_WR_PROCESSING

Description

Interrupt Status Register

Fields

DATRDY

Data Ready
URAD

Unspecified Register Access Detection Status
URAT

Unspecified Register Access:

0 (IDR_WR_PROCESSING): Input Data Register written during the data processing when SMOD=0x2 mode.

1 (ODR_RD_PROCESSING): Output Data Register read during the data processing.

2 (MR_WR_PROCESSING): Mode Register written during the data processing.

3 (ODR_RD_SUBKGEN): Output Data Register read during the sub-keys generation.

4 (MR_WR_SUBKGEN): Mode Register written during the sub-keys generation.

5 (WOR_RD_ACCESS): Write-only register read access.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data