PLLADIV2=NOT_DIV2, MDIV=EQ_PCK, PRES=CLOCK_DIV1, CSS=SLOW_CLK
Master Clock Register
| CSS | Master/Processor Clock Source Selection 0 (SLOW_CLK): Slow Clock is selected 1 (MAIN_CLK): Main Clock is selected 2 (PLLA_CLK): PLLACK/PLLADIV2 is selected 3 (PLLB_CLK): PLLBCK is selected |
| PRES | Master/Processor Clock Prescaler 0 (CLOCK_DIV1): Selected clock 1 (CLOCK_DIV2): Selected clock divided by 2 2 (CLOCK_DIV4): Selected clock divided by 4 3 (CLOCK_DIV8): Selected clock divided by 8 4 (CLOCK_DIV16): Selected clock divided by 16 5 (CLOCK_DIV32): Selected clock divided by 32 6 (CLOCK_DIV64): Selected clock divided by 64 |
| MDIV | Master Clock Division 0 (EQ_PCK): Master Clock is Prescaler Output Clock divided by 1.Warning: SysClk DDR and DDRCK are not available. 1 (PCK_DIV2): Master Clock is Prescaler Output Clock divided by 2.SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. 2 (PCK_DIV4): Master Clock is Prescaler Output Clock divided by 4.SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. 3 (PCK_DIV3): Master Clock is Prescaler Output Clock divided by 3.SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. |
| PLLADIV2 | PLLA divisor by 2 0 (NOT_DIV2): PLLA clock frequency is divided by 1. 1 (DIV2): PLLA clock frequency is divided by 2. |