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Atmel /AT91SAM9G10 /PMC /CKGR_PLLBR

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Interpret as CKGR_PLLBR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DIVB0PLLBCOUNT0OUTB 0MULB0USBDIV

Description

PLL B Register

Fields

DIVB

Divider B
PLLBCOUNT

PLL B Counter
OUTB

PLLB Clock Frequency Range
MULB

PLL Multiplier
USBDIV

Divider for USB Clock

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data