Atmel /AT91SAM9G10 /SDRAMC /CR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0NC0NR0 (NB)NB 0CAS0 (DBW)DBW 0TWR0TRC0TRP0TRCD0TRAS0TXSR

Description

SDRAMC Configuration Register

Fields

NC

Number of Column Bits

NR

Number of Row Bits

NB

Number of Banks

CAS

CAS Latency

DBW

Data Bus Width

TWR

Write Recovery Delay

TRC

Row Cycle Delay

TRP

Row Precharge Delay

TRCD

Row to Column Delay

TRAS

Active to Precharge Delay

TXSR

Exit Self Refresh to Active Delay

Links

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