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Atmel /AT91SAM9G20 /ADC /IDR

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Interpret as IDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EOC0)EOC0 0 (EOC1)EOC1 0 (EOC2)EOC2 0 (EOC3)EOC3 0 (DRDY)DRDY 0 (GOVRE)GOVRE 0 (COMPE)COMPE 0 (ENDRX)ENDRX 0 (RXBUFF)RXBUFF

Description

Interrupt Disable Register

Fields

EOC0

End of Conversion Interrupt Disable 0
EOC1

End of Conversion Interrupt Disable 1
EOC2

End of Conversion Interrupt Disable 2
EOC3

End of Conversion Interrupt Disable 3
DRDY

Data Ready Interrupt Disable
GOVRE

General Overrun Error Interrupt Disable
COMPE

Comparison Event Interrupt Disable
ENDRX

End of Receive Buffer Interrupt Disable
RXBUFF

Receive Buffer Full Interrupt Disable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data