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Atmel /AT91SAM9G25 /PMC /PMC_PCR

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Interpret as PMC_PCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PID0 (CMD)CMD 0 (PERIPH_DIV_MCK)DIV0 (EN)EN

DIV=PERIPH_DIV_MCK

Description

Peripheral Control Register

Fields

PID

Peripheral ID
CMD

Command
DIV

Divisor Value

0 (PERIPH_DIV_MCK): Peripheral clock is MCK

1 (PERIPH_DIV2_MCK): Peripheral clock is MCK/2

2 (PERIPH_DIV4_MCK): Peripheral clock is MCK/4

3 (PERIPH_DIV8_MCK): Peripheral clock is MCK/8
EN

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data