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Atmel /AT91SAM9G25 /UDPHS /EPTCTL0_ISOENDPT

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Interpret as EPTCTL0_ISOENDPT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EPT_ENABL)EPT_ENABL 0 (AUTO_VALID)AUTO_VALID 0 (INTDIS_DMA)INTDIS_DMA 0 (DATAX_RX)DATAX_RX 0 (MDATA_RX)MDATA_RX 0 (ERR_OVFLW)ERR_OVFLW 0 (RXRDY_TXKL)RXRDY_TXKL 0 (TX_COMPLT)TX_COMPLT 0 (TXRDY_TRER)TXRDY_TRER 0 (ERR_FL_ISO)ERR_FL_ISO 0 (ERR_CRC_NTR)ERR_CRC_NTR 0 (ERR_FLUSH)ERR_FLUSH 0 (BUSY_BANK)BUSY_BANK 0 (SHRT_PCKT)SHRT_PCKT

Description

UDPHS Endpoint Control Register (endpoint = 0)

Fields

EPT_ENABL

Endpoint Enable
AUTO_VALID

Packet Auto-Valid Enabled
INTDIS_DMA

Interrupt Disables DMA
DATAX_RX

DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
MDATA_RX

MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
ERR_OVFLW

Overflow Error Interrupt Enabled
RXRDY_TXKL

Received OUT Data Interrupt Enabled
TX_COMPLT

Transmitted IN Data Complete Interrupt Enabled
TXRDY_TRER

TX Packet Ready/Transaction Error Interrupt Enabled
ERR_FL_ISO

Error Flow Interrupt Enabled
ERR_CRC_NTR

ISO CRC Error/Number of Transaction Error Interrupt Enabled
ERR_FLUSH

Bank Flush Error Interrupt Enabled
BUSY_BANK

Busy Bank Interrupt Enabled
SHRT_PCKT

Short Packet Interrupt Enabled

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data