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Atmel /AT91SAM9G25 /UDPHS /EPTCTLDIS5_ISOENDPT

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Interpret as EPTCTLDIS5_ISOENDPT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EPT_DISABL)EPT_DISABL 0 (AUTO_VALID)AUTO_VALID 0 (INTDIS_DMA)INTDIS_DMA 0 (DATAX_RX)DATAX_RX 0 (MDATA_RX)MDATA_RX 0 (ERR_OVFLW)ERR_OVFLW 0 (RXRDY_TXKL)RXRDY_TXKL 0 (TX_COMPLT)TX_COMPLT 0 (TXRDY_TRER)TXRDY_TRER 0 (ERR_FL_ISO)ERR_FL_ISO 0 (ERR_CRC_NTR)ERR_CRC_NTR 0 (ERR_FLUSH)ERR_FLUSH 0 (BUSY_BANK)BUSY_BANK 0 (SHRT_PCKT)SHRT_PCKT

Description

UDPHS Endpoint Control Disable Register (endpoint = 5)

Fields

EPT_DISABL

Endpoint Disable
AUTO_VALID

Packet Auto-Valid Disable
INTDIS_DMA

Interrupts Disable DMA
DATAX_RX

DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
MDATA_RX

MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
ERR_OVFLW

Overflow Error Interrupt Disable
RXRDY_TXKL

Received OUT Data Interrupt Disable
TX_COMPLT

Transmitted IN Data Complete Interrupt Disable
TXRDY_TRER

TX Packet Ready/Transaction Error Interrupt Disable
ERR_FL_ISO

Error Flow Interrupt Disable
ERR_CRC_NTR

ISO CRC Error/Number of Transaction Error Interrupt Disable
ERR_FLUSH

bank flush error Interrupt Disable
BUSY_BANK

Busy Bank Interrupt Disable
SHRT_PCKT

Short Packet Interrupt Disable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data