Atmel /AT91SAM9M11 /DDRSDRC1 /LPR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as LPR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LPCB 0 (CLK_FR)CLK_FR 0PASR0TCR0DS0TIMEOUT 0 (APDE)APDE 0UPD_MR

Description

DDRSDRC Low-power Register

Fields

LPCB

Low-power Command Bit

CLK_FR

Clock Frozen Command Bit

PASR

Partial Array Self Refresh

TCR

Temperature Compensated Self Refresh

DS

Drive Strength

TIMEOUT

Low Power Mode

APDE

Active Power Down Exit Time

UPD_MR

Update Load Mode Register and Extended Mode Register

Links

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