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Atmel /AT91SAM9M11 /SHA /MR

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Interpret as MR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SMOD 0 (PROCDLY)PROCDLY 0 (ALGO)ALGO

Description

Mode Register

Fields

SMOD

Start Mode
PROCDLY

Processing Delay
ALGO

SHA Algorithm

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data