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Atmel /ATSAM3U2E /DMAC /CTRLA1

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Interpret as CTRLA1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BTSIZE0 (BYTE)SRC_WIDTH 0 (BYTE)DST_WIDTH 0 (DONE)DONE

DST_WIDTH=BYTE, SRC_WIDTH=BYTE

Description

DMAC Channel Control A Register (ch_num = 1)

Fields

BTSIZE

Buffer Transfer Size
SRC_WIDTH

Transfer Width for the Source

0 (BYTE): the transfer size is set to 8-bit width

1 (HALF_WORD): the transfer size is set to 16-bit width

2 (WORD): the transfer size is set to 32-bit width
DST_WIDTH

Transfer Width for the Destination

0 (BYTE): the transfer size is set to 8-bit width

1 (HALF_WORD): the transfer size is set to 16-bit width

2 (WORD): the transfer size is set to 32-bit width
DONE

Current Descriptor Stop Command and Transfer Completed Memory Indicator

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data