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Description
Peripheral Control Register
Fields
| PID | |
| CMD | |
| DIV | 0 (PERIPH_DIV_MCK): Peripheral clock is MCK
1 (PERIPH_DIV2_MCK): Peripheral clock is MCK/2
2 (PERIPH_DIV4_MCK): Peripheral clock is MCK/4
|
| EN | |
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