Device DMA Channel Control Register (n = 5)
| CHANN_ENB | Channel Enable Command |
| LDNXT_DSC | Load Next Channel Transfer Descriptor Enable Command |
| END_TR_EN | End of Transfer Enable Control |
| END_B_EN | End of Buffer Enable Control |
| END_TR_IT | End of Transfer Interrupt Enable |
| END_BUFFIT | End of Buffer Interrupt Enable |
| DESC_LD_IT | Descriptor Loaded Interrupt Enable |
| BURST_LCK | Burst Lock Enable |
| BUFF_LENGTH | Buffer Byte Length (Write-only) |