Atmel /ATSAM4SP32A /PPLC /CSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CPOL)CPOL 0 (NCPHA)NCPHA 0 (CSNAAT)CSNAAT 0 (CSAAT)CSAAT 0BITS0SCBR0DLYBS0DLYBCT

Description

Chip Select Register

Fields

CPOL

Clock Polarity

NCPHA

Clock Phase

CSNAAT

Chip Select Not Active After Transfer (Ignored if CSAAT = 1)

CSAAT

Chip Select Active After Transfer

BITS

Bits Per Transfer

SCBR

Serial Clock Baud Rate

DLYBS

Delay Before SPCK

DLYBCT

Delay Between Consecutive Transfers

Links

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