Atmel /ATSAMA5D31 /LCDC /HEOIMR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as HEOIMR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA)DMA 0 (DSCR)DSCR 0 (ADD)ADD 0 (DONE)DONE 0 (OVR)OVR 0 (UDMA)UDMA 0 (UDSCR)UDSCR 0 (UADD)UADD 0 (UDONE)UDONE 0 (UOVR)UOVR 0 (VDMA)VDMA 0 (VDSCR)VDSCR 0 (VADD)VADD 0 (VDONE)VDONE 0 (VOVR)VOVR

Description

High-End Overlay Interrupt Mask Register

Fields

DMA

End of DMA Transfer Interrupt Mask Register

DSCR

Descriptor Loaded Interrupt Mask Register

ADD

Head Descriptor Loaded Interrupt Mask Register

DONE

End of List Interrupt Mask Register

OVR

Overflow Interrupt Mask Register

UDMA

End of DMA Transfer for U or UV Chrominance Component Interrupt Mask Register

UDSCR

Descriptor Loaded for U or UV Chrominance Component Interrupt Mask Register

UADD

Head Descriptor Loaded for U or UV Chrominance Component Mask Register

UDONE

End of List for U or UV Chrominance Component Mask Register

UOVR

Overflow for U Chrominance Interrupt Mask Register

VDMA

End of DMA Transfer for V Chrominance Component Interrupt Mask Register

VDSCR

Descriptor Loaded for V Chrominance Component Interrupt Mask Register

VADD

Head Descriptor Loaded for V Chrominance Component Mask Register

VDONE

End of List for V Chrominance Component Mask Register

VOVR

Overflow for V Chrominance Interrupt Mask Register

Links

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