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Atmel /ATSAMA5D31 /LCDC /OVR1CHSR

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Interpret as OVR1CHSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CHSR)CHSR 0 (UPDATESR)UPDATESR 0 (A2QSR)A2QSR

Description

Overlay 1 Channel Status Register

Fields

CHSR

Channel Status Register
UPDATESR

Update Overlay Attributes In Progress
A2QSR

Add to Queue Pending Register

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data