Atmel /ATSAMA5D31 /LCDC /PPIDR

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Interpret as PPIDR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA)DMA 0 (DSCR)DSCR 0 (ADD)ADD 0 (DONE)DONE

Description

Post Processing Interrupt Disable Register

Fields

DMA

End of DMA Transfer Interrupt Disable Register

DSCR

Descriptor Loaded Interrupt Disable Register

ADD

Head Descriptor Loaded Interrupt Disable Register

DONE

End of List Interrupt Disable Register

Links

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