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Atmel /ATSAMA5D31 /MPDDRC /LPDDR2_CAL_MR4

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Interpret as LPDDR2_CAL_MR4

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0COUNT_CAL0MR4_READ

Description

MPDDRC LPDDR2 Calibration and MR4 Register

Fields

COUNT_CAL

LPDDR2 Calibration Timer Count
MR4_READ

Mode Register 4 Read Interval

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data