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Atmel /ATSAMA5D31 /PWM /SCM

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Interpret as SCM

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYNC0)SYNC0 0 (SYNC1)SYNC1 0 (SYNC2)SYNC2 0 (SYNC3)SYNC3 0 (MODE0)UPDM

UPDM=MODE0

Description

PWM Sync Channels Mode Register

Fields

SYNC0

Synchronous Channel 0
SYNC1

Synchronous Channel 1
SYNC2

Synchronous Channel 2
SYNC3

Synchronous Channel 3
UPDM

Synchronous Channels Update Mode

0 (MODE0): Manual write of double buffer registers and manual update of synchronous channels

1 (MODE1): Manual write of double buffer registers and automatic update of synchronous channels

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data