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Atmel /ATSAMA5D33 /GMAC /TSR

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Interpret as TSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (UBR)UBR 0 (COL)COL 0 (RLE)RLE 0 (TXGO)TXGO 0 (TFC)TFC 0 (TXCOMP)TXCOMP 0 (UND)UND 0 (LCO)LCO 0 (HRESP)HRESP

Description

Transmit Status Register

Fields

UBR

Used Bit Read
COL

Collision Occurred
RLE

Retry Limit Exceeded
TXGO

Transmit Go
TFC

Transmit Frame Corruption due to AHB error
TXCOMP

Transmit Complete
UND

Transmit Under Run
LCO

Late Collision Occurred
HRESP

HRESP Not OK

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data