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Atmel /ATSAMR21E19A /SYSCTRL /DPLLCTRLB

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Interpret as DPLLCTRLB

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DEFAULT)FILTER 0 (LPEN)LPEN 0 (WUF)WUF 0 (REF0)REFCLK 0 (DEFAULT)LTIME0 (LBYPASS)LBYPASS 0DIV

LTIME=DEFAULT, REFCLK=REF0, FILTER=DEFAULT

Description

DPLL Control B

Fields

FILTER

Proportional Integral Filter Selection

0 (DEFAULT): Default filter mode

1 (LBFILT): Low bandwidth filter

2 (HBFILT): High bandwidth filter

3 (HDFILT): High damping filter
LPEN

Low-Power Enable
WUF

Wake Up Fast
REFCLK

Reference Clock Selection

0 (REF0): CLK_DPLL_REF0 clock reference

1 (REF1): CLK_DPLL_REF1 clock reference

2 (GCLK): GCLK_DPLL clock reference
LTIME

Lock Time

0 (DEFAULT): No time-out

4 (8MS): Time-out if no lock within 8 ms

5 (9MS): Time-out if no lock within 9 ms

6 (10MS): Time-out if no lock within 10 ms

7 (11MS): Time-out if no lock within 11 ms
LBYPASS

Lock Bypass
DIV

Clock Divider

Links

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Register License

============================================================================ Atmel Microcontroller Software Support

Copyright © 2016 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the Licence at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data