Atmel /ATSAMR21G16A /SYSCTRL /DPLLSTATUS

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Interpret as DPLLSTATUS

7 43 0 0 00 0 0 0 0 0 0 0 0 (LOCK)LOCK 0 (CLKRDY)CLKRDY 0 (ENABLE)ENABLE 0 (DIV)DIV

Description

DPLL Status

Fields

LOCK

DPLL Lock Status

CLKRDY

Output Clock Ready

ENABLE

DPLL Enable

DIV

Divider Enable

Links

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