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Atmel /ATSAMR21G18A /GCLK /GENCTRL

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Interpret as GENCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ID0 (XOSC)SRC0 (GENEN)GENEN 0 (IDC)IDC 0 (OOV)OOV 0 (OE)OE 0 (DIVSEL)DIVSEL 0 (RUNSTDBY)RUNSTDBY

SRC=XOSC

Description

Generic Clock Generator Control

Fields

ID

Generic Clock Generator Selection
SRC

Source Select

0 (XOSC): XOSC oscillator output

1 (GCLKIN): Generator input pad

2 (GCLKGEN1): Generic clock generator 1 output

3 (OSCULP32K): OSCULP32K oscillator output

4 (OSC32K): OSC32K oscillator output

5 (XOSC32K): XOSC32K oscillator output

6 (OSC8M): OSC8M oscillator output

7 (DFLL48M): DFLL48M output

8 (FDPLL): FDPLL output
GENEN

Generic Clock Generator Enable
IDC

Improve Duty Cycle
OOV

Output Off Value
OE

Output Enable
DIVSEL

Divide Selection
RUNSTDBY

Run in Standby

Links

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Register License

============================================================================ Atmel Microcontroller Software Support

Copyright © 2016 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the Licence at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data