Fujitsu /S6E1A1 /CLOCK /INT_CLR

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Interpret as INT_CLR

7 43 0 0 00 0 0 0 0 0 0 0 0 (MCSC)MCSC 0 (SCSC)SCSC 0 (PCSC)PCSC 0 (FCSC)FCSC

Description

Interrupt Clear Register

Fields

MCSC

Main clock oscillation stabilization wait completion interrupt factor clear bit

SCSC

Sub clock oscillation stabilization wait completion interrupt factor clear bit

PCSC

PLL oscillation stabilization wait completion interrupt factor clear bit

FCSC

Anomalous frequency detection interrupt factor clear bit

Links

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