Fujitsu /S6E1A1 /CLOCK /INT_ENR

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Interpret as INT_ENR

7 43 0 0 00 0 0 0 0 0 0 0 0 (MCSE)MCSE 0 (SCSE)SCSE 0 (PCSE)PCSE 0 (FCSE)FCSE

Description

Interrupt Enable Register

Fields

MCSE

Main clock oscillation stabilization wait completion interrupt enable bit

SCSE

Sub clock oscillation stabilization wait completion interrupt enable bit

PCSE

PLL oscillation stabilization wait completion interrupt enable bit

FCSE

Anomalous frequency detection interrupt enable bit

Links

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