Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/Fujitsu/S6E1A1/CLOCK/SCM_CTL#0x0
System Clock Mode Control Register
High-speed CR clock oscillation enable bit
Main clock oscillation enable bit
Sub clock oscillation enable bit
PLL oscillation enable bit
Master clock switch control bits
https://github.com/cmsis-svd/cmsis-svd-data