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Fujitsu /S6E1A1 /INTREQ /DRQSEL

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Interpret as DRQSEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ADCSCAN0)ADCSCAN0 0 (ADCSCAN1)ADCSCAN1 0 (ADCSCAN2)ADCSCAN2 0 (IRQ0BT0)IRQ0BT0 0 (IRQ0BT2)IRQ0BT2 0 (IRQ0BT4)IRQ0BT4 0 (IRQ0BT6)IRQ0BT6 0 (MFS0RX)MFS0RX 0 (MFS0TX)MFS0TX 0 (MFS1RX)MFS1RX 0 (MFS1TX)MFS1TX 0 (MFS2RX)MFS2RX 0 (MFS2TX)MFS2TX 0 (MFS3RX)MFS3RX 0 (MFS3TX)MFS3TX 0 (MFS4RX)MFS4RX 0 (MFS4TX)MFS4TX 0 (MFS5RX)MFS5RX 0 (MFS5TX)MFS5TX 0 (MFS6RX)MFS6RX 0 (MFS6TX)MFS6TX 0 (MFS7RX)MFS7RX 0 (MFS7TX)MFS7TX 0 (EXINT0)EXINT0 0 (EXINT1)EXINT1 0 (EXINT2)EXINT2 0 (EXINT3)EXINT3

Description

DMA Request Selection Register

Fields

ADCSCAN0

The scan conversion interrupt signal of the A/D converter unit 0 is output as a transfer request to the DMAC
ADCSCAN1

The scan conversion interrupt signal of the A/D converter unit 1 is output as a transfer request to the DMAC
ADCSCAN2

The scan conversion interrupt signal of the A/D converter unit 2 is output as a transfer request to the DMAC
IRQ0BT0

The IRQ0 interrupt signal of the base timer ch.0 is output as a transfer request to the DMAC
IRQ0BT2

The IRQ0 interrupt signal of the base timer ch.2 is output as a transfer request to the DMAC
IRQ0BT4

The IRQ0 interrupt signal of the base timer ch.4 is output as a transfer request to the DMAC
IRQ0BT6

The IRQ0 interrupt signal of the base timer ch.6 is output as a transfer request to the DMAC
MFS0RX

The reception interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC
MFS0TX

The transmission interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC
MFS1RX

The reception interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC
MFS1TX

The transmission interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC
MFS2RX

The reception interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC
MFS2TX

The transmission interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC
MFS3RX

The reception interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC
MFS3TX

The transmission interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC
MFS4RX

The reception interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC
MFS4TX

The transmission interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC
MFS5RX

The reception interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC
MFS5TX

The transmission interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC
MFS6RX

The reception interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC
MFS6TX

The transmission interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC
MFS7RX

The reception interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC
MFS7TX

The transmission interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC
EXINT0

The interrupt signal of the external interrupt ch.0 is output as a transfer request to the DMAC
EXINT1

The interrupt signal of the external interrupt ch.1 is output as a transfer request to the DMAC
EXINT2

The interrupt signal of the external interrupt ch.2 is output as a transfer request to the DMAC
EXINT3

The interrupt signal of the external interrupt ch.3 is output as a transfer request to the DMAC

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data