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Fujitsu /S6E2CC /CRG /APBC0_PSR

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Interpret as APBC0_PSR

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https://regviz.com/r/Fujitsu/S6E2CC/CRG/APBC0_PSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0APBC0

Description

APB0 Prescaler Register

Fields

APBC0

APB0 bus clock frequency division ratio setting bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data