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Fujitsu /S6E2CC /CRG /APBC1_PSR

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Interpret as APBC1_PSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0APBC1 0 (APBC1RST)APBC1RST 0 (APBC1EN)APBC1EN

Description

APB1 Prescaler Register

Fields

APBC1

APB1 bus clock frequency division ratio setting bit
APBC1RST

APB1 bus reset control bit
APBC1EN

APB1 clock enable bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data