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Fujitsu /S6E2CC /CRG /DBWDT_CTL

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Interpret as DBWDT_CTL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DPSWBE)DPSWBE 0 (DPHWBE)DPHWBE

Description

Debug Break Watchdog Timer Control Register

Fields

DPSWBE

SW-WDG debug mode break bit
DPHWBE

HW-WDG debug mode break bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data