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Fujitsu /S6E2CC /CRG /PLL_CTL1

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Interpret as PLL_CTL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLLM0PLLK

Description

PLL Control Register 1

Fields

PLLM

PLL VCO clock frequency division ratio setting bit
PLLK

PLL input clock frequency division ratio setting bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data