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Fujitsu /S6E2CC /CRG /PLL_CTL2

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Interpret as PLL_CTL2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLLN

Description

PLL Control Register 2

Fields

PLLN

PLL feedback frequency division ratio setting bit

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data