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Fujitsu /S6E2CC /CRG /PSW_TMR

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Interpret as PSW_TMR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0POWT0 (PINC)PINC

Description

PLL Clock Stabilization Wait Time Setup Register

Fields

POWT

PLL clock stabilization wait time setup bit
PINC

PLL input clock select bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data