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Fujitsu /S6E2CC /CRG /SWC_PSR

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Interpret as SWC_PSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SWDS

Description

Software Watchdog Clock Prescaler Register

Fields

SWDS

Software watchdog clock frequency division ratio setting bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data