Peripheral Communication Setting Register 0
| CPHA | Clock phase setting bit |
| CPOL | Serial clock polarity setting bit |
| ACES | Serial data transmission/reception timing setting bit |
| RTM | Timing compensation setting bit |
| SSPOL | Slave select polarity setting bit |
| SS2CD | Slave-select-to-clock-start delay time setting bit |
| SDIR | Shift direction setting bit |
| SENDIAN | Endian setting bit |
| CDRS | Clock division ratio setting bits |
| SAFESYNC | Safe synchronization bit |
| WRDSEL | Write or different command deselect time setting bits |
| RDDSEL | Read deselect time setting bits |