Control Register
| FSPL | This sets the polarity of the I2SWS pin |
| FSLN | This specifies the pulse width of I2SWS |
| FSPH | This specifies the phase for I2SWS frame data |
| CPOL | This specifies the I2SCK polarity where drive sampling of the serial data is performed |
| SMPL | This specifies the point where data is sampled |
| RXDIS | This enables or disables the receive function |
| TXDIS | This enables or disables the transmit function |
| MLSB | This sets word bit shift order |
| FRUN | This sets the output mode of the frame sync signal |
| BEXT | When the receive word length is smaller than the FIFO word length, this sets the upper bit extension mode. |
| ECKM | In master mode, this selects the base clock divider. |
| RHLL | This sets the FIFO word configuration to one or two words |
| SBFN | This specifies the subframe configuration (number of subframes) of the frame |
| MSMD | This sets master or slave mode. |
| MSKB | This sets the serial output data of the invalid transmit frames |
| OVHD | Following the valid data of the frame, it can insert OVERHEAD bits to enable adjustment of the frame rate. |
| CKRT | When operating in master mode, this sets the clock division ratio for output. |